This invention relates to integrated circuits (ICs) and data processing systems and their design, in particular to integrated circuit devices having a modular data-flow (data-driven) architecture.
Continuing advances in semiconductor technology have made possible the integration of increasingly complex functionality on a single chip. Single large chips are now capable of performing the functions of entire multi-chip systems of a few years ago. While providing new opportunities, multimillion-gate systems-on-chip pose new challenges to the system designer. In particular, conventional design and verification methodologies are often unacceptably time-consuming for large systems-on-chip.
Hardware design reuse has been proposed as an approach to addressing the challenges of designing large systems. In this approach, functional blocks (also referred to as cores or intellectual property, IP) are pre-designed and tested for reuse in multiple systems. The system designer then integrates multiple such functional blocks to generate a desired system. The cores are often connected to a common bus, and are controlled by a central microcontroller or CPU.
The hardware design reuse approach reduces the redundant re-designing of commonly-used cores for multiple applications. At the same time, the task of interconnecting the cores often makes the system integration relatively difficult. Such integration is particularly difficult for cores having complex and/or core-specific interfaces. Core integration is one of the major challenges in designing large systems integrated on a single chip using the hardware design reuse approach.
U.S. Pat. No. 6,145,073, “Data Flow Integrated Circuit Architecture,” herein incorporated by reference, provides an architecture and design methodology allowing relatively fast and robust design of large systems-on-chip. The described systems are optimized for working in a single context at a time.